1. Field of the Invention
The present invention relates to a multi-layer chip capacitor, and more particularly to a multi-layer chip capacitor having a reduced equivalent serial inductance (ESL) and suitably used in a high-frequency circuit.
2. Description of the Related Art
Generally, a multi-layer chip capacitor (MLCC) comprises a plurality of dielectric layers, referred to as “ceramic green sheets”, and internal electrodes interposed between the dielectric layers. The multi-layer chip capacitor has a small size and a high capacitance, and is easily mounted on a substrate, thus being used as a capacity component of various electric apparatuses. Particularly, the multi-layer chip capacitor is used as a decoupling capacitor arranged in a power supply circuit of an LSI.
In order to prevent the rapid fluctuation of current and stabilize the power circuit, the multi-layer chip capacitor used as the decoupling capacitor must have a low ESL. The above requirement is increased according to the high-frequency and high-current trends of the electric apparatuses. Conventionally, in order to reduce the ESL of the multi-layer chip capacitor, U.S. Pat. No. 5,880,925 proposes that respective lead structures of first internal electrodes are located adjacent respective lead structures of second internal electrodes in an interdigitated arrangement. One example of such an arrangement is shown in FIG. 1a. 
FIG. 1a is an exploded perspective view illustrating a plurality of dielectric layers and internal electrodes employed by a conventional multi-layer chip capacitor. FIG. 1b is a schematic perspective view of the conventional multi-layer chip capacitor manufactured using the internal electrodes of FIG. 1a. With reference to FIG. 1a, a first internal electrode 12 or a second internal electrode 13 is formed on each of a plurality of dielectric sheets 11a to 11h referred to as “ceramic green sheets”. The first and second internal electrodes 12 and 13 have polarities different from each other. The dielectric layers 11a to 11h provided with the internal electrodes 12 and 13 are stacked, thereby producing a capacitor body 11 of a capacitor 10 (See FIG. 1b).
With reference to FIGS. 1a and 1b, leads 14 of the first internal electrodes 12 and leads 15 of the second internal electrodes 13 are connected to respective ones of terminal electrodes 16 and 17. The leads 14 of the first internal electrodes 12 are located adjacent the leads 15 of the second internal electrodes 13 in an interdigitated arrangement. Since the polarities of the voltages supplied to the nearby leads 14 and 15 differ, the magnetic fluxes generated due to the high frequency currents flowing from the terminal electrodes 16 and 17 are canceled out between theses adjoining leads 14 and 15. Therefore, the ESL is reduced.
However, it is difficult to sufficiently reduce the ESL of the above conventional multi-layer chip capacitor. Although the interdigitated arrangement of the leads is used, the ESL reduction effect is partially acquired only between the adjoining leads. The lead structure itself acts as a significant factor increasing the ESL of the capacitor.